Hardware Efficient Architecture with Variable Block Size for Motion Estimation
Video coding standards such as MPEG-x and H.26x incorporate variable block size motion estimation (VBSME) which is highly time consuming and extremely complex from hardware implementation perspective due to huge computation. In this paper, we have discussed basic aspects of video coding and studied...
Saved in:
Main Authors: | Nehal N. Shah, Harikrishna Singapuri, Upena D. Dalal |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2016-01-01
|
Series: | Journal of Electrical and Computer Engineering |
Online Access: | http://dx.doi.org/10.1155/2016/5091519 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Resource Efficient Hardware Architecture for Fast Computation of Running Max/Min Filters
by: Cesar Torres-Huitzil
Published: (2013-01-01) -
Hardware-efficient preparation of architecture-specific graph states on near-term quantum computers
by: Sebastian Brandhofer, et al.
Published: (2025-01-01) -
Vastus lateralis nerve block for knee hardware removal
by: Jibran Ikram, et al.
Published: (2025-01-01) -
An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network
by: Arati Kumari Shah, et al.
Published: (2023-01-01) -
Modular Self-Reconfigurable Robotic Systems: A Survey on Hardware Architectures
by: S. Sankhar Reddy Chennareddy, et al.
Published: (2017-01-01)