Via placement optimization for a group of wires
Most PCB design CAD systems offer a limited number of “patterns” for the via placement on a bus (group of wires) which would be either a single- or a double-row placement. This article demonstrates the incorrectness of such limitations, because in this case the mounting space is used not in an optim...
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| Format: | Article |
| Language: | English |
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Politehperiodika
2015-06-01
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| Series: | Tekhnologiya i Konstruirovanie v Elektronnoi Apparature |
| Subjects: | |
| Online Access: | https://tkea.com.ua/index.php/journal/article/view/278 |
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| _version_ | 1849312697025298432 |
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| author | K. A. Knop S. Yu. Luzin |
| author_facet | K. A. Knop S. Yu. Luzin |
| author_sort | K. A. Knop |
| collection | DOAJ |
| description | Most PCB design CAD systems offer a limited number of “patterns” for the via placement on a bus (group of wires) which would be either a single- or a double-row placement. This article demonstrates the incorrectness of such limitations, because in this case the mounting space is used not in an optimal way. The paper presents the optimum solution for a certain type of problems on via placement when changing the layer of a bus. The solution suggests a regular (periodic) arrangement, but with a multi-row placement. The calculation of the parameters for optimal placement is narrowed, in general, to finding the number of via rows with which the area of a topological fragment is minimal. |
| format | Article |
| id | doaj-art-e9637a2c00ce4ad1828fc169ec8b5d5a |
| institution | Kabale University |
| issn | 2225-5818 2309-9992 |
| language | English |
| publishDate | 2015-06-01 |
| publisher | Politehperiodika |
| record_format | Article |
| series | Tekhnologiya i Konstruirovanie v Elektronnoi Apparature |
| spelling | doaj-art-e9637a2c00ce4ad1828fc169ec8b5d5a2025-08-20T03:53:01ZengPolitehperiodikaTekhnologiya i Konstruirovanie v Elektronnoi Apparature2225-58182309-99922015-06-012–3101410.15222/TKEA2015.2-3.10278Via placement optimization for a group of wiresK. A. Knop0S. Yu. Luzin1«Eremex» Ltd, Saint Petersburg, Russia«Eremex» Ltd, Saint Petersburg, RussiaMost PCB design CAD systems offer a limited number of “patterns” for the via placement on a bus (group of wires) which would be either a single- or a double-row placement. This article demonstrates the incorrectness of such limitations, because in this case the mounting space is used not in an optimal way. The paper presents the optimum solution for a certain type of problems on via placement when changing the layer of a bus. The solution suggests a regular (periodic) arrangement, but with a multi-row placement. The calculation of the parameters for optimal placement is narrowed, in general, to finding the number of via rows with which the area of a topological fragment is minimal.https://tkea.com.ua/index.php/journal/article/view/278printed wiringviagroup of wires |
| spellingShingle | K. A. Knop S. Yu. Luzin Via placement optimization for a group of wires Tekhnologiya i Konstruirovanie v Elektronnoi Apparature printed wiring via group of wires |
| title | Via placement optimization for a group of wires |
| title_full | Via placement optimization for a group of wires |
| title_fullStr | Via placement optimization for a group of wires |
| title_full_unstemmed | Via placement optimization for a group of wires |
| title_short | Via placement optimization for a group of wires |
| title_sort | via placement optimization for a group of wires |
| topic | printed wiring via group of wires |
| url | https://tkea.com.ua/index.php/journal/article/view/278 |
| work_keys_str_mv | AT kaknop viaplacementoptimizationforagroupofwires AT syuluzin viaplacementoptimizationforagroupofwires |