Via placement optimization for a group of wires
Most PCB design CAD systems offer a limited number of “patterns” for the via placement on a bus (group of wires) which would be either a single- or a double-row placement. This article demonstrates the incorrectness of such limitations, because in this case the mounting space is used not in an optim...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Politehperiodika
2015-06-01
|
| Series: | Tekhnologiya i Konstruirovanie v Elektronnoi Apparature |
| Subjects: | |
| Online Access: | https://tkea.com.ua/index.php/journal/article/view/278 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|