A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology
A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of g...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | Advances in Materials Science and Engineering |
| Online Access: | http://dx.doi.org/10.1155/2013/905686 |
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| _version_ | 1832550036432486400 |
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| author | Chih-Yao Huang Fu-Chien Chiu |
| author_facet | Chih-Yao Huang Fu-Chien Chiu |
| author_sort | Chih-Yao Huang |
| collection | DOAJ |
| description | A substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case. |
| format | Article |
| id | doaj-art-e1224b1a0ff04d5cb36db7cf24c51c5e |
| institution | Kabale University |
| issn | 1687-8434 1687-8442 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Advances in Materials Science and Engineering |
| spelling | doaj-art-e1224b1a0ff04d5cb36db7cf24c51c5e2025-02-03T06:07:53ZengWileyAdvances in Materials Science and Engineering1687-84341687-84422013-01-01201310.1155/2013/905686905686A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer TechnologyChih-Yao Huang0Fu-Chien Chiu1Department of Electronics Engineering, Chien Hsin University of Science and Technology, No. 229 Chien Hsin Road, Zhongli, Taoyuan 320, TaiwanDepartment of Electronic Engineering, Ming Chuan University, No. 5 De Ming Road, GuiShan, Taoyuan 333, TaiwanA substrate-and-gate triggering scheme which utilizes dynamic threshold principle is proposed for an ESD NMOS structure. This scheme enhances the device reliability performance in terms of higher second breakdown current and both reduced holding voltage/triggering voltage as well as elimination of gate over driven effect. The simple resistance and RC substrate-and-gate triggering NMOS structure with various resistance/capacitance values totally exhibit superior ESD reliability than the gate-grounded NMOS (GGNMOS) devices by 18~29%. The substrate-and-gate triggering scheme in combination with special substrate pickup styles also shows excellent enhancement when compared with the GGNMOS cases of the same pickup styles. The substrate-and-gate triggering NMOS with butting substrate pickup style is better than the general butting case by 28~30%, whereas the substrate-and-gate triggering NMOS with inserted substrate pickup style is 3.5 times superior to the general inserted case.http://dx.doi.org/10.1155/2013/905686 |
| spellingShingle | Chih-Yao Huang Fu-Chien Chiu A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology Advances in Materials Science and Engineering |
| title | A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology |
| title_full | A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology |
| title_fullStr | A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology |
| title_full_unstemmed | A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology |
| title_short | A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology |
| title_sort | substrate and gate triggering nmos device for high esd reliability in deep submicrometer technology |
| url | http://dx.doi.org/10.1155/2013/905686 |
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