Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA
This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2014-01-01
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| Series: | International Journal of Distributed Sensor Networks |
| Online Access: | https://doi.org/10.1155/2014/815378 |
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| _version_ | 1832553294568882176 |
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| author | Abdul Waheed Malik Benny Thörnberg Muhammad Imran Najeem Lawal |
| author_facet | Abdul Waheed Malik Benny Thörnberg Muhammad Imran Najeem Lawal |
| author_sort | Abdul Waheed Malik |
| collection | DOAJ |
| description | This paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27 MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13 mW at 86 frames per second. |
| format | Article |
| id | doaj-art-d4961859e2154f269f269a0c08bd6283 |
| institution | Kabale University |
| issn | 1550-1477 |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Distributed Sensor Networks |
| spelling | doaj-art-d4961859e2154f269f269a0c08bd62832025-02-03T05:54:31ZengWileyInternational Journal of Distributed Sensor Networks1550-14772014-01-011010.1155/2014/815378815378Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGAAbdul Waheed MalikBenny ThörnbergMuhammad ImranNajeem LawalThis paper describes a hardware architecture for real-time image component labeling and the computation of image component feature descriptors. These descriptors are object related properties used to describe each image component. Embedded machine vision systems demand a robust performance and power efficiency as well as minimum area utilization, depending on the deployed application. In the proposed architecture, the hardware modules for component labeling and feature calculation run in parallel. A CMOS image sensor (MT9V032), operating at a maximum clock frequency of 27 MHz, was used to capture the images. The architecture was synthesized and implemented on a Xilinx Spartan-6 FPGA. The developed architecture is capable of processing 390 video frames per second of size 640 × 480 pixels. Dynamic power consumption is 13 mW at 86 frames per second.https://doi.org/10.1155/2014/815378 |
| spellingShingle | Abdul Waheed Malik Benny Thörnberg Muhammad Imran Najeem Lawal Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA International Journal of Distributed Sensor Networks |
| title | Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA |
| title_full | Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA |
| title_fullStr | Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA |
| title_full_unstemmed | Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA |
| title_short | Hardware Architecture for Real-Time Computation of Image Component Feature Descriptors on a FPGA |
| title_sort | hardware architecture for real time computation of image component feature descriptors on a fpga |
| url | https://doi.org/10.1155/2014/815378 |
| work_keys_str_mv | AT abdulwaheedmalik hardwarearchitectureforrealtimecomputationofimagecomponentfeaturedescriptorsonafpga AT bennythornberg hardwarearchitectureforrealtimecomputationofimagecomponentfeaturedescriptorsonafpga AT muhammadimran hardwarearchitectureforrealtimecomputationofimagecomponentfeaturedescriptorsonafpga AT najeemlawal hardwarearchitectureforrealtimecomputationofimagecomponentfeaturedescriptorsonafpga |