Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing
Abstract The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading‐one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to a...
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| Format: | Article |
| Language: | English |
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Wiley
2021-07-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12019 |
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| author | Mohammad Saeed Ansari Shyama Gandhi Bruce F. Cockburn Jie Han |
| author_facet | Mohammad Saeed Ansari Shyama Gandhi Bruce F. Cockburn Jie Han |
| author_sort | Mohammad Saeed Ansari |
| collection | DOAJ |
| description | Abstract The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading‐one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2d. Additionally, a scaling scheme is proposed that scales up the input N < 2d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one ‘1’ in that half; otherwise, the less significant half is passed. Our simulation results show that the 32‐bit LOD III can be up to 2.8× more energy‐efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs. |
| format | Article |
| id | doaj-art-d343739228504534945aba40579138ce |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-d343739228504534945aba40579138ce2025-02-03T01:29:41ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-07-0115424125010.1049/cdt2.12019Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computingMohammad Saeed Ansari0Shyama Gandhi1Bruce F. Cockburn2Jie Han3Department of Electrical and Computer Engineering University of Alberta Edmonton AB CanadaDepartment of Electrical and Computer Engineering University of Alberta Edmonton AB CanadaDepartment of Electrical and Computer Engineering University of Alberta Edmonton AB CanadaDepartment of Electrical and Computer Engineering University of Alberta Edmonton AB CanadaAbstract The logarithmic number system (LNS) can be used to simplify the computation of arithmetic functions, such as multiplication. This article proposes three leading‐one detectors (LODs) to speed up the binary logarithm calculation in the LNS. The first LOD (LOD I) uses a single fixed value to approximate the d least significant bits (LSBs) in the outputs of the LOD. The second design (LOD II) partitions the d LSBs into smaller fields and uses a multiplexer to select the closest approximation to the exact value. These two LODs help with error cancellation as they introduce signed errors for inputs N < 2d. Additionally, a scaling scheme is proposed that scales up the input N < 2d to avoid large approximation errors. Finally, an improved exact LOD (LOD III) is proposed that only passes half of the input N to the LOD; the more significant half is passed if there is at least one ‘1’ in that half; otherwise, the less significant half is passed. Our simulation results show that the 32‐bit LOD III can be up to 2.8× more energy‐efficient than existing designs in the literature. The Mitchell logarithmic multiplier and a neural network are considered to further illustrate the practicality of the proposed designs.https://doi.org/10.1049/cdt2.12019approximation theorydetector circuitsenergy conservationfloating point arithmeticlogic designlow‐power electronics |
| spellingShingle | Mohammad Saeed Ansari Shyama Gandhi Bruce F. Cockburn Jie Han Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing IET Computers & Digital Techniques approximation theory detector circuits energy conservation floating point arithmetic logic design low‐power electronics |
| title | Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing |
| title_full | Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing |
| title_fullStr | Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing |
| title_full_unstemmed | Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing |
| title_short | Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing |
| title_sort | fast and low power leading one detectors for energy efficient logarithmic computing |
| topic | approximation theory detector circuits energy conservation floating point arithmetic logic design low‐power electronics |
| url | https://doi.org/10.1049/cdt2.12019 |
| work_keys_str_mv | AT mohammadsaeedansari fastandlowpowerleadingonedetectorsforenergyefficientlogarithmiccomputing AT shyamagandhi fastandlowpowerleadingonedetectorsforenergyefficientlogarithmiccomputing AT brucefcockburn fastandlowpowerleadingonedetectorsforenergyefficientlogarithmiccomputing AT jiehan fastandlowpowerleadingonedetectorsforenergyefficientlogarithmiccomputing |