Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers
High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter appl...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10767763/ |
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| author | Seoyoung Jang Jaewon Lee Yujin Choi Donggeun Kim Gain Kim |
| author_facet | Seoyoung Jang Jaewon Lee Yujin Choi Donggeun Kim Gain Kim |
| author_sort | Seoyoung Jang |
| collection | DOAJ |
| description | High-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed. |
| format | Article |
| id | doaj-art-d2a1e2fe5b384d62b2e8d08faf99891f |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-d2a1e2fe5b384d62b2e8d08faf99891f2025-01-25T00:03:20ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01429030410.1109/OJSSCS.2024.350669210767763Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based EqualizersSeoyoung Jang0https://orcid.org/0009-0008-1056-0470Jaewon Lee1https://orcid.org/0000-0003-3222-5020Yujin Choi2https://orcid.org/0009-0006-2364-8768Donggeun Kim3https://orcid.org/0009-0008-9512-7915Gain Kim4https://orcid.org/0000-0002-3680-8816Department of Electrical Engineering and Computer Science, DGIST, Daegu, South KoreaDepartment of Electrical Engineering and Computer Science, DGIST, Daegu, South KoreaDepartment of Electrical Engineering and Computer Science, DGIST, Daegu, South KoreaDepartment of Electrical Engineering and Computer Science, DGIST, Daegu, South KoreaDepartment of Electrical Engineering and Computer Science, DGIST, Daegu, South KoreaHigh-speed wireline data transceivers (TRX) with analog-to-digital converter (ADC) followed by digital signal processor (DSP) on the receiver (RX) equalizer became popular for applications requiring >100-Gb/s per-lane data rate over long-reach (LR) channels, especially for datacenter applications. With the digital-to-analog converter (DAC)-based transmitter (TX), including DSP-based TX signal processing, the overall structure of DAC/ADC-DSP-based wireline TRXs became similar to modulator/demodulator (MODEM). This article overviews DAC/ADC-DSP-based wireline transceivers and analyzes their subblocks, such as analog front-end (AFE), DSP techniques, and their implementation, focusing on the equalizer datapath. Recently published relevant articles are briefly reviewed, and insights from prior arts are provided. TRX architectures for energy- and bandwidth-efficient DAC/ADC-DSP-based TRX using modulation schemes beyond 4-level pulse amplitude modulation (PAM-4) are also reviewed and discussed. In addition, hardware-based serializer–deserializer simulation and real-time emulation systems for rapid architecture and design verification are reviewed.https://ieeexplore.ieee.org/document/10767763/4-level pulse amplitude modulation (PAM-4)ADC-based RXanalog-to-digital converter (ADC)DAC/ADC-DSP-based TRXdigital signal processor (DSP) equalizerdigital-to-analog converter (DAC) |
| spellingShingle | Seoyoung Jang Jaewon Lee Yujin Choi Donggeun Kim Gain Kim Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers IEEE Open Journal of the Solid-State Circuits Society 4-level pulse amplitude modulation (PAM-4) ADC-based RX analog-to-digital converter (ADC) DAC/ADC-DSP-based TRX digital signal processor (DSP) equalizer digital-to-analog converter (DAC) |
| title | Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers |
| title_full | Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers |
| title_fullStr | Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers |
| title_full_unstemmed | Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers |
| title_short | Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers |
| title_sort | recent advances in ultrahigh speed wireline receivers with adc dsp based equalizers |
| topic | 4-level pulse amplitude modulation (PAM-4) ADC-based RX analog-to-digital converter (ADC) DAC/ADC-DSP-based TRX digital signal processor (DSP) equalizer digital-to-analog converter (DAC) |
| url | https://ieeexplore.ieee.org/document/10767763/ |
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