Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator

Disturbance‐Aware On‐Chip Training with Mitigation Schemes for Massively Parallel Computing in Analog Deep Learning Accelerator

Abstract On‐chip training in analog in‐memory computing (AIMC) holds great promise for reducing data latency and enabling user‐specific learning. However, analog synaptic devices face significant challenges, particularly during parallel weight updates in crossbar arrays, where non‐uniform programmin...

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Bibliographic Details
Main Authors: Jaehyeon Kang, Jongun Won, Narae Han, Sangjun Hong, Jee‐Eun Yang, Sangwook Kim, Sangbum Kim
Format: Article
Language:English
Published: Wiley 2025-06-01
Series:Advanced Science
Subjects:
Analog in‐memory computing
Disturbance
Disturbance‐aware training
Half‐selected
IGZO TFT
Neuromorphic
Online Access:https://doi.org/10.1002/advs.202417635
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https://doi.org/10.1002/advs.202417635

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