Design of SoC/SIP simulation acceleration based on distributed computing
With the continuous growth of IC design scale and complexity, traditional EDA verification is more and more restricted especially for sub-system and SoC full chip level simulation efficiency. To efficiently and effectively find and debug RTL problems and ensure the IC delivery quality and time to ma...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2024-01-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000163436 |
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