Hardware Implementation of 128-Bit AES Image Encryption with Low Power Techniques on FPGA to VHDL
This paper describes the implementation of a low power and high-speed encryption algorithm with high throughput for encrypting the image. Therefore, we select a highly secured symmetric key encryption algorithm AES(Advanced Encryption Standard), in order to decrease the power using retiming and gli...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
OICC Press
2024-02-01
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| Series: | Majlesi Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://oiccpress.com/mjee/article/view/5218 |
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