High level modeling of Dynamic Reconfigurable FPGAs
As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2009-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2009/408605 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832556160666828800 |
|---|---|
| author | Imran Rafiq Quadri Samy Meftali Jean-Luc Dekeyser |
| author_facet | Imran Rafiq Quadri Samy Meftali Jean-Luc Dekeyser |
| author_sort | Imran Rafiq Quadri |
| collection | DOAJ |
| description | As System-on-Chip (SoC) based embedded systems
have become a defacto industry standard, their overall design
complexity has increased exponentially in recent years,
necessitating the introduction of new seamless methodologies
and tools to handle the SoC codesign aspects. This paper
presents a novel SoC co-design methodology based on Model
Driven Engineering and the Modeling and Analysis
of Real-Time and Embedded Systems (MARTE) standard, permitting us
to raise the abstraction levels and allows to model fine grain
reconfigurable architectures such as FPGAs. Extensions of this
methodology have enabled us to integrate new features such as
Partial Dynamic Reconfiguration supported by Modern FPGAs.
The overall objective is to carry out system modeling at a high
abstraction level expressed in a graphical language like
Unified Modeling Language (UML) and afterwards transformation
of these models automatically generate the necessary code for
FPGA synthesis. |
| format | Article |
| id | doaj-art-c261e83cab794b028617990bd3ead020 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2009-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-c261e83cab794b028617990bd3ead0202025-02-03T05:46:11ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092009-01-01200910.1155/2009/408605408605High level modeling of Dynamic Reconfigurable FPGAsImran Rafiq Quadri0Samy Meftali1Jean-Luc Dekeyser2INRIA Lille Nord Europe, Laboratoire d'Informatique Fondamentale de Lille (LIFL), Centre national de la recherche scientifique (CNRS), University of Lille, 59650 Lille, FranceINRIA Lille Nord Europe, Laboratoire d'Informatique Fondamentale de Lille (LIFL), Centre national de la recherche scientifique (CNRS), University of Lille, 59650 Lille, FranceINRIA Lille Nord Europe, Laboratoire d'Informatique Fondamentale de Lille (LIFL), Centre national de la recherche scientifique (CNRS), University of Lille, 59650 Lille, FranceAs System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.http://dx.doi.org/10.1155/2009/408605 |
| spellingShingle | Imran Rafiq Quadri Samy Meftali Jean-Luc Dekeyser High level modeling of Dynamic Reconfigurable FPGAs International Journal of Reconfigurable Computing |
| title | High level modeling of Dynamic Reconfigurable FPGAs |
| title_full | High level modeling of Dynamic Reconfigurable FPGAs |
| title_fullStr | High level modeling of Dynamic Reconfigurable FPGAs |
| title_full_unstemmed | High level modeling of Dynamic Reconfigurable FPGAs |
| title_short | High level modeling of Dynamic Reconfigurable FPGAs |
| title_sort | high level modeling of dynamic reconfigurable fpgas |
| url | http://dx.doi.org/10.1155/2009/408605 |
| work_keys_str_mv | AT imranrafiqquadri highlevelmodelingofdynamicreconfigurablefpgas AT samymeftali highlevelmodelingofdynamicreconfigurablefpgas AT jeanlucdekeyser highlevelmodelingofdynamicreconfigurablefpgas |