A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor
This paper presents a method for processing and digitizing the current signal information output from biosensors and a hardware Artificial Intelligence (AI) model design that classifies data using low-power and compact AI algorithms to minimize the high-power consumption and on chip area of the Conv...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/11008630/ |
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| author | Geon-Hoe Kim Dong-Gyun Kim Sung-Jae Lee Jong-Han Kim Da-Yeong An Hyejin Kim Young-Gun Pu Heejeong Jasmine Lee Jun-Eun Park Kang-Yoon Lee |
| author_facet | Geon-Hoe Kim Dong-Gyun Kim Sung-Jae Lee Jong-Han Kim Da-Yeong An Hyejin Kim Young-Gun Pu Heejeong Jasmine Lee Jun-Eun Park Kang-Yoon Lee |
| author_sort | Geon-Hoe Kim |
| collection | DOAJ |
| description | This paper presents a method for processing and digitizing the current signal information output from biosensors and a hardware Artificial Intelligence (AI) model design that classifies data using low-power and compact AI algorithms to minimize the high-power consumption and on chip area of the Convolutional Neural Network (CNN) models used in biosensors. The dataset was built using a data sampling method that digitizes the current signal values from the biosensor by sampling them 16 times with a 16-bit Analog-to-Digital Converter (ADC), enabling feature extraction in advance. To reduce power consumption and area, a BNN-MLP model without an extraction layer was designed, and to improve accuracy, a dense layer was added to the final layer. This approach enhances accuracy while using binary weights. The BNN-MLP model was designed using TensorFlow for the software model and implemented in hardware at the Register Transfer Level (RTL). To verify the similarity between the hardware-implemented BNN-MLP model and the software BNN-MLP model, classification was performed on a test dataset of 1,000 samples using a Field Programmable Gate Array (FPGA), and the classification accuracy for each class was compared. When the BNN-MLP model is implemented on an FPGA, it utilizes 7,994 Look-Up Tables (LUT) and 9,780 Flip-Flops (FF), occupying fewer resources compared to previous studies. Additionally, it operates at a lower power consumption of 0.157 W, demonstrating the highest power efficiency performance of 407.6 GOPS/W. Finally, the inference time for a single data point was 0.018 ms, which is much faster than in previous studies, confirming its potential for low-power and compact applications in biosensors. |
| format | Article |
| id | doaj-art-c25885e0691a4db59855f1e9a71ee9d1 |
| institution | OA Journals |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-c25885e0691a4db59855f1e9a71ee9d12025-08-20T02:34:38ZengIEEEIEEE Access2169-35362025-01-0113907419075210.1109/ACCESS.2025.357220111008630A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a BiosensorGeon-Hoe Kim0https://orcid.org/0009-0002-3045-505XDong-Gyun Kim1Sung-Jae Lee2https://orcid.org/0009-0008-7771-856XJong-Han Kim3Da-Yeong An4https://orcid.org/0009-0001-4869-2857Hyejin Kim5Young-Gun Pu6Heejeong Jasmine Lee7https://orcid.org/0000-0001-5153-756XJun-Eun Park8https://orcid.org/0000-0001-6345-7903Kang-Yoon Lee9https://orcid.org/0000-0001-9777-6953Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Artificial Intelligence, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaSKAIChips, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaSKAIChips, Suwon, South KoreaSKAIChips, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaThis paper presents a method for processing and digitizing the current signal information output from biosensors and a hardware Artificial Intelligence (AI) model design that classifies data using low-power and compact AI algorithms to minimize the high-power consumption and on chip area of the Convolutional Neural Network (CNN) models used in biosensors. The dataset was built using a data sampling method that digitizes the current signal values from the biosensor by sampling them 16 times with a 16-bit Analog-to-Digital Converter (ADC), enabling feature extraction in advance. To reduce power consumption and area, a BNN-MLP model without an extraction layer was designed, and to improve accuracy, a dense layer was added to the final layer. This approach enhances accuracy while using binary weights. The BNN-MLP model was designed using TensorFlow for the software model and implemented in hardware at the Register Transfer Level (RTL). To verify the similarity between the hardware-implemented BNN-MLP model and the software BNN-MLP model, classification was performed on a test dataset of 1,000 samples using a Field Programmable Gate Array (FPGA), and the classification accuracy for each class was compared. When the BNN-MLP model is implemented on an FPGA, it utilizes 7,994 Look-Up Tables (LUT) and 9,780 Flip-Flops (FF), occupying fewer resources compared to previous studies. Additionally, it operates at a lower power consumption of 0.157 W, demonstrating the highest power efficiency performance of 407.6 GOPS/W. Finally, the inference time for a single data point was 0.018 ms, which is much faster than in previous studies, confirming its potential for low-power and compact applications in biosensors.https://ieeexplore.ieee.org/document/11008630/Binary neural networksartificial intelligencesensor data classificationdata samplingFPGAlow-power |
| spellingShingle | Geon-Hoe Kim Dong-Gyun Kim Sung-Jae Lee Jong-Han Kim Da-Yeong An Hyejin Kim Young-Gun Pu Heejeong Jasmine Lee Jun-Eun Park Kang-Yoon Lee A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor IEEE Access Binary neural networks artificial intelligence sensor data classification data sampling FPGA low-power |
| title | A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor |
| title_full | A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor |
| title_fullStr | A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor |
| title_full_unstemmed | A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor |
| title_short | A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor |
| title_sort | low power memory integrated hardware bnn mlp model on an fpga for current signals in a biosensor |
| topic | Binary neural networks artificial intelligence sensor data classification data sampling FPGA low-power |
| url | https://ieeexplore.ieee.org/document/11008630/ |
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