A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor

A Low Power Memory-Integrated Hardware BNN-MLP Model on an FPGA for Current Signals in a Biosensor

This paper presents a method for processing and digitizing the current signal information output from biosensors and a hardware Artificial Intelligence (AI) model design that classifies data using low-power and compact AI algorithms to minimize the high-power consumption and on chip area of the Conv...

Full description

Saved in:
Bibliographic Details
Main Authors: Geon-Hoe Kim, Dong-Gyun Kim, Sung-Jae Lee, Jong-Han Kim, Da-Yeong An, Hyejin Kim, Young-Gun Pu, Heejeong Jasmine Lee, Jun-Eun Park, Kang-Yoon Lee
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Binary neural networks
artificial intelligence
sensor data classification
data sampling
FPGA
low-power
Online Access:https://ieeexplore.ieee.org/document/11008630/
Tags: Add Tag
No Tags, Be the first to tag this record!

Internet

https://ieeexplore.ieee.org/document/11008630/

Similar Items