Secure Scan Architecture for Enhanced Testability and Resistance Against Side-Channel Attacks in Cryptographic ICs
Traditional scan-based Design for Testability (DFT) techniques give full visibility of internal nodes, which makes them vulnerable to side-channel attacks where the confidential data is compromised. These attacks exploit physical attributes of power, timing, electromagnetic radiation, and fault resp...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11020643/ |
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