Lee, S., Park, J. H., & Lee, Y. Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip. IEEE.
Chicago Style (17th ed.) CitationLee, Seung-Han, Jin Hwan Park, and Young-Woo Lee. Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip. IEEE.
MLA (9th ed.) CitationLee, Seung-Han, et al. Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip. IEEE.
Warning: These citations may not always be 100% accurate.