Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip
Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conducted using Automatic Test Equipment (ATE) along with test infrastructures such as the Prober Interface Board (PIB), sig...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10897964/ |
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