Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)

The demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consum...

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Bibliographic Details
Main Authors: D. Satyanarayana, M. Chennakesavulu, N. Fouzia Sulthana, K. Upendra, D. Sashidhar, K. Ramachandra Reddy, N. Naga Sai Vikranth, V. Devendra
Format: Article
Language:English
Published: Polish Academy of Sciences 2025-06-01
Series:International Journal of Electronics and Telecommunications
Subjects:
low power
full adder
multiplier
delay
passtransistor
Online Access:https://journals.pan.pl/Content/135268/18-5058-Satyanarayana-sk.pdf
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