Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)
The demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consum...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Polish Academy of Sciences
2025-06-01
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| Series: | International Journal of Electronics and Telecommunications |
| Subjects: | |
| Online Access: | https://journals.pan.pl/Content/135268/18-5058-Satyanarayana-sk.pdf |
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