Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)
The demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consum...
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| Format: | Article |
| Language: | English |
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Polish Academy of Sciences
2025-06-01
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| Series: | International Journal of Electronics and Telecommunications |
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| Online Access: | https://journals.pan.pl/Content/135268/18-5058-Satyanarayana-sk.pdf |
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| author | D. Satyanarayana M. Chennakesavulu N. Fouzia Sulthana K. Upendra D. Sashidhar K. Ramachandra Reddy N. Naga Sai Vikranth V. Devendra |
| author_facet | D. Satyanarayana M. Chennakesavulu N. Fouzia Sulthana K. Upendra D. Sashidhar K. Ramachandra Reddy N. Naga Sai Vikranth V. Devendra |
| author_sort | D. Satyanarayana |
| collection | DOAJ |
| description | The demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consumption, operational speed and silicon area usage. The proposed multiplier using PTL-based logic gates to generate partial products, followed by a reduction tree and a final addition stage, all optimized for performance and efficiency. Key design challenges, such as voltage degradation and level restoration inherent in PTL circuits, is addressed through carefully designed voltage restoration techniques and custom PTL cells. The architecture is compared against conventional CMOS-based multipliers to demonstrate its superiority in terms of power efficiency and speed. All the circuits are simulated using ECAD tools to analyze the power, delay, area and Power-Delay-Product (PDP) of the multiplier to highlight a substantial reduction in power consumption and a faster operation, making the PTL-based multiplier an ideal circuit for high-performance and low-power applications in modern digital systems. The proposed work contributes to the field of low-power digital design by showcasing the potential of PTL in creating multipliers which are not only efficient but also scalable for future technology nodes. |
| format | Article |
| id | doaj-art-bb1d3f85979444beac5f45ef5f50935b |
| institution | Kabale University |
| issn | 2081-8491 2300-1933 |
| language | English |
| publishDate | 2025-06-01 |
| publisher | Polish Academy of Sciences |
| record_format | Article |
| series | International Journal of Electronics and Telecommunications |
| spelling | doaj-art-bb1d3f85979444beac5f45ef5f50935b2025-08-20T03:24:36ZengPolish Academy of SciencesInternational Journal of Electronics and Telecommunications2081-84912300-19332025-06-01vol. 71No 2483488https://doi.org/10.24425/ijet.2025.153595Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic)D. Satyanarayana0M. Chennakesavulu1N. Fouzia Sulthana2K. Upendra3D. Sashidhar4K. Ramachandra Reddy5N. Naga Sai Vikranth6V. Devendra7Dept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaDept. of ECE, Rajeev Gandhi Memorial College of Engineering and Technology, Andhra Pradesh, IndiaThe demand for low-power, high-speed, and area efficient digital circuits has driven the exploration of alternative logic families such as Pass Transistor Logic (PTL). The design of a multiplier circuit that leverages the inherent advantages of PTL to achieve significant improvements in power consumption, operational speed and silicon area usage. The proposed multiplier using PTL-based logic gates to generate partial products, followed by a reduction tree and a final addition stage, all optimized for performance and efficiency. Key design challenges, such as voltage degradation and level restoration inherent in PTL circuits, is addressed through carefully designed voltage restoration techniques and custom PTL cells. The architecture is compared against conventional CMOS-based multipliers to demonstrate its superiority in terms of power efficiency and speed. All the circuits are simulated using ECAD tools to analyze the power, delay, area and Power-Delay-Product (PDP) of the multiplier to highlight a substantial reduction in power consumption and a faster operation, making the PTL-based multiplier an ideal circuit for high-performance and low-power applications in modern digital systems. The proposed work contributes to the field of low-power digital design by showcasing the potential of PTL in creating multipliers which are not only efficient but also scalable for future technology nodes.https://journals.pan.pl/Content/135268/18-5058-Satyanarayana-sk.pdflow powerfull addermultiplierdelaypasstransistor |
| spellingShingle | D. Satyanarayana M. Chennakesavulu N. Fouzia Sulthana K. Upendra D. Sashidhar K. Ramachandra Reddy N. Naga Sai Vikranth V. Devendra Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) International Journal of Electronics and Telecommunications low power full adder multiplier delay passtransistor |
| title | Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) |
| title_full | Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) |
| title_fullStr | Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) |
| title_full_unstemmed | Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) |
| title_short | Design of efficient multiplier with low power and high-speed using PTL (Pass Transistor Logic) |
| title_sort | design of efficient multiplier with low power and high speed using ptl pass transistor logic |
| topic | low power full adder multiplier delay passtransistor |
| url | https://journals.pan.pl/Content/135268/18-5058-Satyanarayana-sk.pdf |
| work_keys_str_mv | AT dsatyanarayana designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT mchennakesavulu designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT nfouziasulthana designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT kupendra designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT dsashidhar designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT kramachandrareddy designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT nnagasaivikranth designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic AT vdevendra designofefficientmultiplierwithlowpowerandhighspeedusingptlpasstransistorlogic |