Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width
In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall...
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IEEE
2025-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/11021571/ |
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| author | Sanguk Lee Jinsu Jeong Jongseo Park Seunghwan Lee Junjong Lee Yonghwan Ahn Minchan Kim Rock-Hyun Baek |
| author_facet | Sanguk Lee Jinsu Jeong Jongseo Park Seunghwan Lee Junjong Lee Yonghwan Ahn Minchan Kim Rock-Hyun Baek |
| author_sort | Sanguk Lee |
| collection | DOAJ |
| description | In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall between N/P-type devices. However, FSFETs have inherent drawbacks: one side of the channel and source/drain (S/D) inevitably interfaces with the wall, leading to a compromised electrical performance compared with that of NSFETs. Moreover, when the gate edge aligns with the wall on one side, sufficient GE and GC margins are still required on the opposite side. To address these challenges, we propose patterned multi-wall NSFETs (MW-NSFETs) comprising patterned walls on both sides of the channel, which facilitate gate-all-around channel formation and wrap-around contact, resulting in superior DC behavior. Furthermore, CH can be scaled down as both sides of the gate edges self-align with the patterned multiwall. Consequently, MW-NSFETs yield a higher Ion (4.65%) and lower RC delay (6.2%) at a 12.04% smaller CH than FSFETs. Moreover, at the circuit level, the MW-NSFETs exhibited a higher oscillation frequency compared with FSFETs. Thus, MW-NSFETs represent viable devices for sub-2-nm nodes, meeting the stringent criteria for high performance and minimal CH values in logic applications. |
| format | Article |
| id | doaj-art-b682a5a5cbe748b69bc2d4531947a02f |
| institution | OA Journals |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-b682a5a5cbe748b69bc2d4531947a02f2025-08-20T02:32:49ZengIEEEIEEE Access2169-35362025-01-0113993559936510.1109/ACCESS.2025.357626511021571Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut WidthSanguk Lee0https://orcid.org/0000-0002-8932-6626Jinsu Jeong1Jongseo Park2https://orcid.org/0000-0003-2881-5650Seunghwan Lee3https://orcid.org/0000-0003-3137-9335Junjong Lee4https://orcid.org/0000-0002-0513-8784Yonghwan Ahn5https://orcid.org/0009-0004-7381-8441Minchan Kim6https://orcid.org/0009-0000-4701-4504Rock-Hyun Baek7https://orcid.org/0000-0002-6175-8101Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaDepartment of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, South KoreaIn nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall between N/P-type devices. However, FSFETs have inherent drawbacks: one side of the channel and source/drain (S/D) inevitably interfaces with the wall, leading to a compromised electrical performance compared with that of NSFETs. Moreover, when the gate edge aligns with the wall on one side, sufficient GE and GC margins are still required on the opposite side. To address these challenges, we propose patterned multi-wall NSFETs (MW-NSFETs) comprising patterned walls on both sides of the channel, which facilitate gate-all-around channel formation and wrap-around contact, resulting in superior DC behavior. Furthermore, CH can be scaled down as both sides of the gate edges self-align with the patterned multiwall. Consequently, MW-NSFETs yield a higher Ion (4.65%) and lower RC delay (6.2%) at a 12.04% smaller CH than FSFETs. Moreover, at the circuit level, the MW-NSFETs exhibited a higher oscillation frequency compared with FSFETs. Thus, MW-NSFETs represent viable devices for sub-2-nm nodes, meeting the stringent criteria for high performance and minimal CH values in logic applications.https://ieeexplore.ieee.org/document/11021571/Forksheet field-effect transistors (FSFETs)nanosheet FETs (NSFETs)patterned wallcell height (CH)performance optimizationtechnology computer-aided design (TCAD) |
| spellingShingle | Sanguk Lee Jinsu Jeong Jongseo Park Seunghwan Lee Junjong Lee Yonghwan Ahn Minchan Kim Rock-Hyun Baek Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width IEEE Access Forksheet field-effect transistors (FSFETs) nanosheet FETs (NSFETs) patterned wall cell height (CH) performance optimization technology computer-aided design (TCAD) |
| title | Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width |
| title_full | Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width |
| title_fullStr | Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width |
| title_full_unstemmed | Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width |
| title_short | Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width |
| title_sort | patterned multi wall nanosheet fets for sustainable scaling zero gate extension with minimal gate cut width |
| topic | Forksheet field-effect transistors (FSFETs) nanosheet FETs (NSFETs) patterned wall cell height (CH) performance optimization technology computer-aided design (TCAD) |
| url | https://ieeexplore.ieee.org/document/11021571/ |
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