Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width

Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width

In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. In contrast, forksheet FETs (FSFETs) enable aggressive CH reduction by introducing a dielectric wall...

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Bibliographic Details
Main Authors: Sanguk Lee, Jinsu Jeong, Jongseo Park, Seunghwan Lee, Junjong Lee, Yonghwan Ahn, Minchan Kim, Rock-Hyun Baek
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Forksheet field-effect transistors (FSFETs)
nanosheet FETs (NSFETs)
patterned wall
cell height (CH)
performance optimization
technology computer-aided design (TCAD)
Online Access:https://ieeexplore.ieee.org/document/11021571/
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https://ieeexplore.ieee.org/document/11021571/

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