Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs
Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50 Ω resistance. As it is analytically proven,...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
OICC Press
2024-02-01
|
| Series: | Majlesi Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://oiccpress.com/mjee/article/view/5212 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1850283761511432192 |
|---|---|
| author | Ehsan Kargaran Mohammad Javad Zavarei Nahid Fatahi Seyedeh Sara Hassani Khalil Mafinezhad Hooman Nabovati |
| author_facet | Ehsan Kargaran Mohammad Javad Zavarei Nahid Fatahi Seyedeh Sara Hassani Khalil Mafinezhad Hooman Nabovati |
| author_sort | Ehsan Kargaran |
| collection | DOAJ |
| description | Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50 Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFETâs input resistance. The effect of each input impedance matching on the amplifierâs noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage. |
| format | Article |
| id | doaj-art-b3294fa0ba8d490d833478eacaabd021 |
| institution | OA Journals |
| issn | 2345-377X 2345-3796 |
| language | English |
| publishDate | 2024-02-01 |
| publisher | OICC Press |
| record_format | Article |
| series | Majlesi Journal of Electrical Engineering |
| spelling | doaj-art-b3294fa0ba8d490d833478eacaabd0212025-08-20T01:47:43ZengOICC PressMajlesi Journal of Electrical Engineering2345-377X2345-37962024-02-0163Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAsEhsan Kargaran0Mohammad Javad Zavarei1Nahid Fatahi2Seyedeh Sara Hassani3Khalil Mafinezhad4Hooman Nabovati5sadjad institue of higher education, mashhadMicroelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, IranMicroelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, IranMicroelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, IranSadjad Institute of Higher Education, Mashhad, IranDepartment of Electrical Engineering, Sadjad Institute of Higher Education, MashhadDesign and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50 Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFETâs input resistance. The effect of each input impedance matching on the amplifierâs noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage.https://oiccpress.com/mjee/article/view/5212reliability. Technical feasibility |
| spellingShingle | Ehsan Kargaran Mohammad Javad Zavarei Nahid Fatahi Seyedeh Sara Hassani Khalil Mafinezhad Hooman Nabovati Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs Majlesi Journal of Electrical Engineering reliability. Technical feasibility |
| title | Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs |
| title_full | Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs |
| title_fullStr | Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs |
| title_full_unstemmed | Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs |
| title_short | Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs |
| title_sort | design issues for low voltage low power cmos folded cascode lnas |
| topic | reliability. Technical feasibility |
| url | https://oiccpress.com/mjee/article/view/5212 |
| work_keys_str_mv | AT ehsankargaran designissuesforlowvoltagelowpowercmosfoldedcascodelnas AT mohammadjavadzavarei designissuesforlowvoltagelowpowercmosfoldedcascodelnas AT nahidfatahi designissuesforlowvoltagelowpowercmosfoldedcascodelnas AT seyedehsarahassani designissuesforlowvoltagelowpowercmosfoldedcascodelnas AT khalilmafinezhad designissuesforlowvoltagelowpowercmosfoldedcascodelnas AT hoomannabovati designissuesforlowvoltagelowpowercmosfoldedcascodelnas |