Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI
A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for ope...
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MDPI AG
2025-01-01
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| Series: | Chips |
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| Online Access: | https://www.mdpi.com/2674-0729/4/1/4 |
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| author | Jeff Dix |
| author_facet | Jeff Dix |
| author_sort | Jeff Dix |
| collection | DOAJ |
| description | A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. |
| format | Article |
| id | doaj-art-ae9960ed9e694b3f9e0be409dd032d19 |
| institution | OA Journals |
| issn | 2674-0729 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Chips |
| spelling | doaj-art-ae9960ed9e694b3f9e0be409dd032d192025-08-20T02:11:04ZengMDPI AGChips2674-07292025-01-0141410.3390/chips4010004Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOIJeff Dix0Department of Electrical Engineering and Computer Science, University of Arkansas, Fayetteville, AR 72701, USAA low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz.https://www.mdpi.com/2674-0729/4/1/4current starvedlow powerhigh speedMinch cascodeadderinverter |
| spellingShingle | Jeff Dix Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI Chips current starved low power high speed Minch cascode adder inverter |
| title | Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI |
| title_full | Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI |
| title_fullStr | Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI |
| title_full_unstemmed | Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI |
| title_short | Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI |
| title_sort | low power high speed adder circuit utilizing current starved inverters in 22 nm fdsoi |
| topic | current starved low power high speed Minch cascode adder inverter |
| url | https://www.mdpi.com/2674-0729/4/1/4 |
| work_keys_str_mv | AT jeffdix lowpowerhighspeedaddercircuitutilizingcurrentstarvedinvertersin22nmfdsoi |