Low-Power, High-Speed Adder Circuit Utilizing Current-Starved Inverters in 22 nm FDSOI
A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for ope...
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| Main Author: | |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-01-01
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| Series: | Chips |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2674-0729/4/1/4 |
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