Effect of Gate Length Scaling on Various Performance Parameters in DG-FinFETs: a Simulation Study
This paper presents a simulation study on the gate length scaling of a double gate (DG) FinFET. To achieve channel lengths smaller than 20 nm, innovative device architectures will be necessary to continue the benefits previously acquired through scaling. In order to obtain desirable control of short...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Sumy State University
2012-10-01
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| Series: | Журнал нано- та електронної фізики |
| Subjects: | |
| Online Access: | http://jnep.sumdu.edu.ua/download/numbers/2012/3/articles/jnep_2012_V4_03007.pdf |
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