High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped delay-lines (TDLs) are simple to implement but require careful design decisions for high precision and linearity. Although vari...
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2024-01-01
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| author | Lorenzo Castelvero Ignacio H. Lopez Grande Valerio Pruneri |
| author_facet | Lorenzo Castelvero Ignacio H. Lopez Grande Valerio Pruneri |
| author_sort | Lorenzo Castelvero |
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| description | In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped delay-lines (TDLs) are simple to implement but require careful design decisions for high precision and linearity. Although various implementation strategies have been explored in TDC literature across different FPGA technology nodes, the 16-nm node has only recently begun to receive attention. The goal of this study is to leverage a 16-nm FPGA for TDL-TDCs with the requirement of maintaining implementation simplicity while ensuring top-tier performance. We investigated, combined, and optimized various state-of-the-art TDL techniques using an AMD-Xilinx Zynq Ultrascale+ RFSoC. The 16-nm node offers logic buffers (CARRY8) with low propagation delay, ideal for the construction of TDLs. We designed multi-channel TDCs utilizing both single and multiple carry chain TDLs. Propagating a single signal edge allows the use of a simple, bubble-free ones-counting encoder. Buffer redundancy subdivides the bins of the code density histogram, whose linearity is further enhanced by bin decimation. The optimal placement of the TDL elements is considered, together with the sampling clock frequency and source. We demonstrate the capabilities of the TDCs in terms of full-scale range (FSR), dead time, nominal resolution (LSB), RMS precision, differential and integral nonlinearity, hardware utilization, and power consumption. This method leads to TDCs that are simple to implement yet excel in performance, linearity, and sampling rate. For example, we propose a 4-chain TDC achieving LSB < 4 ps, single shot precision (SSP) < 3 ps, DNL < 1 LSB and INL < 2 LSB. |
| format | Article |
| id | doaj-art-9ca4145557eb47a7881b4cc2b1b631b6 |
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| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| spelling | doaj-art-9ca4145557eb47a7881b4cc2b1b631b62025-08-20T01:47:58ZengIEEEIEEE Access2169-35362024-01-011214956914957910.1109/ACCESS.2024.347729510711168High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGALorenzo Castelvero0https://orcid.org/0000-0002-3145-5214Ignacio H. Lopez Grande1Valerio Pruneri2Institut de Ciencies Fotoniques (ICFO), Barcelona Institute of Science and Technology, Barcelona, SpainInstitut de Ciencies Fotoniques (ICFO), Barcelona Institute of Science and Technology, Barcelona, SpainInstitut de Ciencies Fotoniques (ICFO), Barcelona Institute of Science and Technology, Barcelona, SpainIn recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped delay-lines (TDLs) are simple to implement but require careful design decisions for high precision and linearity. Although various implementation strategies have been explored in TDC literature across different FPGA technology nodes, the 16-nm node has only recently begun to receive attention. The goal of this study is to leverage a 16-nm FPGA for TDL-TDCs with the requirement of maintaining implementation simplicity while ensuring top-tier performance. We investigated, combined, and optimized various state-of-the-art TDL techniques using an AMD-Xilinx Zynq Ultrascale+ RFSoC. The 16-nm node offers logic buffers (CARRY8) with low propagation delay, ideal for the construction of TDLs. We designed multi-channel TDCs utilizing both single and multiple carry chain TDLs. Propagating a single signal edge allows the use of a simple, bubble-free ones-counting encoder. Buffer redundancy subdivides the bins of the code density histogram, whose linearity is further enhanced by bin decimation. The optimal placement of the TDL elements is considered, together with the sampling clock frequency and source. We demonstrate the capabilities of the TDCs in terms of full-scale range (FSR), dead time, nominal resolution (LSB), RMS precision, differential and integral nonlinearity, hardware utilization, and power consumption. This method leads to TDCs that are simple to implement yet excel in performance, linearity, and sampling rate. For example, we propose a 4-chain TDC achieving LSB < 4 ps, single shot precision (SSP) < 3 ps, DNL < 1 LSB and INL < 2 LSB.https://ieeexplore.ieee.org/document/10711168/Analog-to-digital converter (ADC)field-programmable gate array (FPGA)tapped delay-line (TDL)time-to-digital converter (TDC) |
| spellingShingle | Lorenzo Castelvero Ignacio H. Lopez Grande Valerio Pruneri High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA IEEE Access Analog-to-digital converter (ADC) field-programmable gate array (FPGA) tapped delay-line (TDL) time-to-digital converter (TDC) |
| title | High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA |
| title_full | High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA |
| title_fullStr | High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA |
| title_full_unstemmed | High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA |
| title_short | High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA |
| title_sort | high performance time to digital conversion on a 16 nm ultrascale fpga |
| topic | Analog-to-digital converter (ADC) field-programmable gate array (FPGA) tapped delay-line (TDL) time-to-digital converter (TDC) |
| url | https://ieeexplore.ieee.org/document/10711168/ |
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