High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA
In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). Tapped delay-lines (TDLs) are simple to implement but require careful design decisions for high precision and linearity. Although vari...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10711168/ |
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