ESTIMATION OF TOPOGRAPHIC DEFECTS DIMENSIONS OF SEMICONDUCTOR SILICON STRUCTURES
The effect of non-flatness of semiconductor wafers on characteristics of manufactured devices is shown through defocusing of an image of a topological layout of a structure being formed and through reduction of resolution at photolithographic processing. For quality control of non-flatness the Makyo...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Belarusian National Technical University
2018-03-01
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| Series: | Приборы и методы измерений |
| Subjects: | |
| Online Access: | https://pimi.bntu.by/jour/article/view/370 |
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