Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM

The probability of timing failure in SRAM accessing becomes unacceptably high at low voltages, which makes the SRAM become the bottleneck of the system performance. Recently proposed timing speculation SRAM (SSRAM) can access bit cells much earlier than the conservative time margin and detect the po...

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Bibliographic Details
Main Authors: Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Cacheline remapping
low-voltage cache
near-threshold voltage
replacement policy
timing speculation SRAM
Online Access:https://ieeexplore.ieee.org/document/8789418/
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https://ieeexplore.ieee.org/document/8789418/

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