Efficient Realization of BCD Multipliers Using FPGAs
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2017/2410408 |
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