Fast and Accurate Cross-PVT Full-Chip Leakage Power Estimation With Multi-Task Learning
As semiconductor technology continues to scale, power consumption has become a primary focus of researchers and engineers. In particular, cross-PVT (Process, Voltage, and Temperature) full-chip leakage power estimation is urgently necessary, as it provides crucial guidance for power delivery network...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10985761/ |
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| Summary: | As semiconductor technology continues to scale, power consumption has become a primary focus of researchers and engineers. In particular, cross-PVT (Process, Voltage, and Temperature) full-chip leakage power estimation is urgently necessary, as it provides crucial guidance for power delivery network design and low-power design strategies and ensures efficient chip design. To address this challenge, we propose an Artificial Neural Network (ANN) model that efficiently integrates data from multiple PVT and provides accurate estimation, given the limited data available for training. This approach enables full-chip leakage power estimation using only one critical cell at one operating state. Our method has been validated using data from a 14 nm industrial FinFET technology node. Compared to the traditional simulation-based method, our method can achieve around 1.76% relative error on average and largely reduced turnaround time, considering all cell types and states. In this case, our method outperforms previous leakage power estimation techniques which fail to provide accurate estimation in low temperature range. When focusing solely on one type of critical cell, the method delivers further acceleration, while maintaining 8.5% maximum relative error. |
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| ISSN: | 2169-3536 |