Error Correction Codes for Double Burst Errors Correction in Memories
This paper addresses the issue of double burst errors occurring in memories and presents the design of corresponding error correction codes (ECC). The proposed ECCs can correct up to two burst errors simultaneously, each up to 4-bit. The errors’ positions are randomly distributed across a...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/11072165/ |
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| author | He Liu Liyi Xiao Tianqi Wang Jiaqiang Li Jie Li |
| author_facet | He Liu Liyi Xiao Tianqi Wang Jiaqiang Li Jie Li |
| author_sort | He Liu |
| collection | DOAJ |
| description | This paper addresses the issue of double burst errors occurring in memories and presents the design of corresponding error correction codes (ECC). The proposed ECCs can correct up to two burst errors simultaneously, each up to 4-bit. The errors’ positions are randomly distributed across any bit within the codeword. The proposed coding scheme is designed with FUEC and syndrome-based decoding. Then the scheme is implemented in hardware with Verilog HDL, utilizing parallel decoding techniques to minimize the latency and parity bits’ number. Comparative evaluations on hardware overheads are conducted for ECCs with the correction capabilities of double burst errors. To minimize the hardware overhead associated with codes with high correction requirements, bit interleaving techniques are applied, further reducing codec area, power, and delay. The ECCs are proved to demonstrate excellent performance in correcting double burst errors, with optimized hardware efficiency. |
| format | Article |
| id | doaj-art-82037fe2926f48459ea93f5cf8e03dac |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-82037fe2926f48459ea93f5cf8e03dac2025-08-20T03:29:03ZengIEEEIEEE Access2169-35362025-01-011311662111663110.1109/ACCESS.2025.358622611072165Error Correction Codes for Double Burst Errors Correction in MemoriesHe Liu0https://orcid.org/0000-0002-9196-4213Liyi Xiao1https://orcid.org/0000-0003-1486-6377Tianqi Wang2https://orcid.org/0000-0002-3039-9038Jiaqiang Li3https://orcid.org/0000-0001-5163-1484Jie Li4Microelectronics Center, Harbin Institute of Technology, Harbin, Heilongjiang, ChinaMicroelectronics Center, Harbin Institute of Technology, Harbin, Heilongjiang, ChinaSpace Environment Simulation Research Infrastructure (SESRI), Harbin Institute of Technology, Harbin, Heilongjiang, ChinaInstitute No.25 of the Second Academy China Aerospace Science and Industry Corporation Ltd., Beijing, ChinaMEMS Center, Harbin Institute of Technology, Harbin, Heilongjiang, ChinaThis paper addresses the issue of double burst errors occurring in memories and presents the design of corresponding error correction codes (ECC). The proposed ECCs can correct up to two burst errors simultaneously, each up to 4-bit. The errors’ positions are randomly distributed across any bit within the codeword. The proposed coding scheme is designed with FUEC and syndrome-based decoding. Then the scheme is implemented in hardware with Verilog HDL, utilizing parallel decoding techniques to minimize the latency and parity bits’ number. Comparative evaluations on hardware overheads are conducted for ECCs with the correction capabilities of double burst errors. To minimize the hardware overhead associated with codes with high correction requirements, bit interleaving techniques are applied, further reducing codec area, power, and delay. The ECCs are proved to demonstrate excellent performance in correcting double burst errors, with optimized hardware efficiency.https://ieeexplore.ieee.org/document/11072165/Double burst errorerror correction codesinterleavinglow hardware overhead |
| spellingShingle | He Liu Liyi Xiao Tianqi Wang Jiaqiang Li Jie Li Error Correction Codes for Double Burst Errors Correction in Memories IEEE Access Double burst error error correction codes interleaving low hardware overhead |
| title | Error Correction Codes for Double Burst Errors Correction in Memories |
| title_full | Error Correction Codes for Double Burst Errors Correction in Memories |
| title_fullStr | Error Correction Codes for Double Burst Errors Correction in Memories |
| title_full_unstemmed | Error Correction Codes for Double Burst Errors Correction in Memories |
| title_short | Error Correction Codes for Double Burst Errors Correction in Memories |
| title_sort | error correction codes for double burst errors correction in memories |
| topic | Double burst error error correction codes interleaving low hardware overhead |
| url | https://ieeexplore.ieee.org/document/11072165/ |
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