Properties of Bilayer Zr- and Sm-Oxide Gate Dielectric on 4H-SiC Substrate Under Varying Nitrogen and Oxygen Concentrations

This work systematically analyses the electrical and structural properties of a bilayer gate dielectric composed of Sm<sub>2</sub>O<sub>3</sub> and ZrO<sub>2</sub> on a 4H-SiC substrate. The bilayer thin film was fabricated using a sputtering process, followed by...

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Main Authors: Ahmad Hafiz Jafarul Tarek, Tahsin Ahmed Mozaffor Onik, Chin Wei Lai, Bushroa Abdul Razak, Chia Ching Kee, Yew Hoong Wong
Format: Article
Language:English
Published: MDPI AG 2025-05-01
Series:Ceramics
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Online Access:https://www.mdpi.com/2571-6131/8/2/49
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Summary:This work systematically analyses the electrical and structural properties of a bilayer gate dielectric composed of Sm<sub>2</sub>O<sub>3</sub> and ZrO<sub>2</sub> on a 4H-SiC substrate. The bilayer thin film was fabricated using a sputtering process, followed by a dry oxidation step with an adjusted oxygen-to-nitrogen (O<sub>2</sub>:N<sub>2</sub>) gas concentration ratio. XRD analysis validated formation of an amorphous structure with a monoclinic phase for both Sm<sub>2</sub>O<sub>3</sub> and ZrO<sub>2</sub> dielectric thin films. High-resolution transmission emission (HRTEM) analysis verified the cross-section of fabricated stacking layers, confirmed physical oxide thickness around 12.08–13.35 nm, and validated the amorphous structure. Meanwhile, XPS confirmed the presence of more stoichiometric dielectric oxide formation for oxidized/nitrided O<sub>2</sub>:N<sub>2</sub>-incorporated samples, and more sub-stochiometric thin films for samples only oxidized in ambient O<sub>2</sub>. The oxidation/nitridation processes with N<sub>2</sub> incorporation influenced the band offsets and revealed conduction band offsets (CBOs) ranging from 2.24 to 2.79 eV. The affected charge movement and influenced electrical performance where optimized samples with gas concentration ratio of 90% O<sub>2</sub>:10% N<sub>2</sub> achieved the highest electrical breakdown field of 10.1 MV cm<sup>−1</sup> at a leakage current density of 10<sup>−6</sup> A cm<sup>−2</sup>. This gate stack also improved key parameters such as the effective dielectric constant (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow></msub></mrow></semantics></math></inline-formula>) up to 29.75, effective oxide charge (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mrow><mi>Q</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow></msub></mrow></semantics></math></inline-formula>), average interface trap density (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mrow><mi>D</mi></mrow><mrow><mi>i</mi><mi>t</mi></mrow></msub></mrow></semantics></math></inline-formula>), and slow trap density (STD). The bilayer gate stack of Sm<sub>2</sub>O<sub>3</sub> and ZrO<sub>2</sub> revealed potential attractive characteristics as a candidate for high-<i>k</i> gate dielectric applications in metal-oxide-semiconductor (MOS)-based devices.
ISSN:2571-6131