An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization

An In-Memory-Computing Binary Neural Network Architecture With In-Memory Batch Normalization

This paper describes an in-memory computing architecture that combines full-precision computation for the first and last layers of a neural network while employing binary weights and input activations for the intermediate layers. This unique approach presents an efficient and effective solution for...

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Bibliographic Details
Main Authors: Prathamesh Prashant Rege, Ming Yin, Sanjay Parihar, Joseph Versaggi, Shashank Nemawarkar
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Batch normalization
binary neural network
edge device
in-memory computing
process variation
SRAM
Online Access:https://ieeexplore.ieee.org/document/10639963/
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