Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration

Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration

Optimizing hardware accelerators in high-level synthesis (HLS) relies on design space exploration (DSE), which involves experimenting with different pragma options and trading off hardware cost and performance metrics (HCPMs) to identify Pareto-optimal solutions. The exponential growth of the design...

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Bibliographic Details
Main Authors: Pouya Taghipour, Eric Granger, Yves Blaquiere
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Electronic design automation (EDA)
high-level synthesis (HLS)
design space exploration (DSE)
machine learning (ML)
graph neural networks (GNN)
field-programmable gate array (FPGA)
Online Access:https://ieeexplore.ieee.org/document/10772109/
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https://ieeexplore.ieee.org/document/10772109/

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