Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)
This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-cryst...
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IEEE
2025-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10906432/ |
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| author | Sandeep Semwal Pin Su |
| author_facet | Sandeep Semwal Pin Su |
| author_sort | Sandeep Semwal |
| collection | DOAJ |
| description | This work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-crystalline HZO ferroelectric (FE). Results show a suppressed improvement with MFMIS topology over the MFIS topology in the subthreshold region if implemented with the CFET architecture due to the CFET-specific common-gate structure. We also propose an alternative MFMIS NC-CFET design with the FE stacked only at the top of the device (~5.3 times lower FE area compared to conventional MFMIS NC-CFET), which can significantly improve the capacitance matching and subthreshold swing provided an FE layer with relatively higher remnant polarization is used. In addition, a design guideline to optimize MFIS NC-CFET is also highlighted. Our study may provide insights into device design for future energy-efficient electronics. |
| format | Article |
| id | doaj-art-7491d5b98a404176b86fe1fd9be9bad6 |
| institution | DOAJ |
| issn | 2168-6734 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-7491d5b98a404176b86fe1fd9be9bad62025-08-20T02:52:59ZengIEEEIEEE Journal of the Electron Devices Society2168-67342025-01-011315416010.1109/JEDS.2025.354631410906432Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)Sandeep Semwal0https://orcid.org/0000-0003-1182-4737Pin Su1https://orcid.org/0000-0002-8213-4103Institute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanInstitute of Electronics, National Yang Ming Chiao Tung University, Hsinchu, TaiwanThis work assesses and analyzes negative-capacitance CFETs (NC-CFETs) with metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) configurations through experimentally calibrated Landau-Khalatnikov model for an ultrathin (1.5 nm) single-crystalline HZO ferroelectric (FE). Results show a suppressed improvement with MFMIS topology over the MFIS topology in the subthreshold region if implemented with the CFET architecture due to the CFET-specific common-gate structure. We also propose an alternative MFMIS NC-CFET design with the FE stacked only at the top of the device (~5.3 times lower FE area compared to conventional MFMIS NC-CFET), which can significantly improve the capacitance matching and subthreshold swing provided an FE layer with relatively higher remnant polarization is used. In addition, a design guideline to optimize MFIS NC-CFET is also highlighted. Our study may provide insights into device design for future energy-efficient electronics.https://ieeexplore.ieee.org/document/10906432/Metal-ferroelectric-metal-insulator-semiconductor (MFMIS)metal-ferroelectric-insulatorsemiconductor (MFIS)complementary-FET (CFET)negative-capacitance FET (NCFET) |
| spellingShingle | Sandeep Semwal Pin Su Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) IEEE Journal of the Electron Devices Society Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) metal-ferroelectric-insulatorsemiconductor (MFIS) complementary-FET (CFET) negative-capacitance FET (NCFET) |
| title | Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) |
| title_full | Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) |
| title_fullStr | Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) |
| title_full_unstemmed | Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) |
| title_short | Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET) |
| title_sort | insights into design optimization of negative capacitance complementary fet cfet |
| topic | Metal-ferroelectric-metal-insulator-semiconductor (MFMIS) metal-ferroelectric-insulatorsemiconductor (MFIS) complementary-FET (CFET) negative-capacitance FET (NCFET) |
| url | https://ieeexplore.ieee.org/document/10906432/ |
| work_keys_str_mv | AT sandeepsemwal insightsintodesignoptimizationofnegativecapacitancecomplementaryfetcfet AT pinsu insightsintodesignoptimizationofnegativecapacitancecomplementaryfetcfet |