Efficient Prefetch and Issue Scheduling Approaches for Simultaneous Multithreading Applied to Superscalar RISC-V Processor
Thread level parallelism (TLP) is a common approach to achieve parallelism where Instruction level parallelism (ILP) is insufficient. Hardware multithreading is a prevalent approach in the micro-architecture layer for tolerating long events such as memory access, mispredictions, and accelerators lat...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10879006/ |
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