A low time mismatch sampling method for time-interleaved ADC
To cope with the performance degradation caused by time mismatch in time-interleaved analog-to-digital converters, an efficient hierarchical series sampling method was proposed. The idea of this sampling method is to aggregate the clock sources related to sampling accuracy at the main sampling switc...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2025-02-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000170240 |
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