Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate

This work explores the integration of strained-channel silicon n-MOSFET with GaN drain using the dual-step selective area epitaxial growth of GaN process, enabling CMOS-compatible, fully selective GaN growth with an excellent GaN/Si interface while adopting a GaN-drain-first manufacturing strategy t...

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Main Authors: Cheng-Jun Huang, Shuo Hwai, Tsai-Fu Chung, Chien-Nan Hsiao, Bo-Cheng Lin, Hung-Ching Tsai, Chi Huang Lui, Edward Yi Chang, Mau-Chung Frank Chang
Format: Article
Language:English
Published: AIP Publishing LLC 2025-05-01
Series:AIP Advances
Online Access:http://dx.doi.org/10.1063/5.0264613
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author Cheng-Jun Huang
Shuo Hwai
Tsai-Fu Chung
Chien-Nan Hsiao
Bo-Cheng Lin
Hung-Ching Tsai
Chi Huang Lui
Edward Yi Chang
Mau-Chung Frank Chang
author_facet Cheng-Jun Huang
Shuo Hwai
Tsai-Fu Chung
Chien-Nan Hsiao
Bo-Cheng Lin
Hung-Ching Tsai
Chi Huang Lui
Edward Yi Chang
Mau-Chung Frank Chang
author_sort Cheng-Jun Huang
collection DOAJ
description This work explores the integration of strained-channel silicon n-MOSFET with GaN drain using the dual-step selective area epitaxial growth of GaN process, enabling CMOS-compatible, fully selective GaN growth with an excellent GaN/Si interface while adopting a GaN-drain-first manufacturing strategy to accommodate thermal budget constraints. After GaN growth and device fabrication, the Si n-MOSFET with a GaN drain exhibited a strained channel, as the epitaxial GaN acts as a stressor, inducing tensile strain in silicon near the GaN drain and enhancing the device’s low-field mobility. Atomic-resolution scanning transmission electron microscopy with strain mapping confirmed the strain effects, while electrical measurements demonstrated a mobility enhancement from 103.8 to 119.8 cm2 V−1 s−1. The integrated GaN drain offers a high breakdown electric field and excellent optoelectronic properties, making it highly promising for high-power and high-frequency system-on-chip technologies, as well as for integration with laser diodes as a drain. These findings highlight the strong potential of GaN-drain Si n-MOSFETs for radio-frequency power amplifier applications and pave the way for advancements in radar, radio, and optoelectronic circuits and systems.
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spelling doaj-art-6567441105084cbcb7f238aa3ecd49912025-08-20T03:19:43ZengAIP Publishing LLCAIP Advances2158-32262025-05-01155055011055011-510.1063/5.0264613Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrateCheng-Jun Huang0Shuo Hwai1Tsai-Fu Chung2Chien-Nan Hsiao3Bo-Cheng Lin4Hung-Ching Tsai5Chi Huang Lui6Edward Yi Chang7Mau-Chung Frank Chang8International College of Semiconductor Technology National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanDepartment of Electrical and Computer Engineering, University of California, Los Angeles (UCLA), Los Angeles, California 90095, USADepartment of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanTaiwan Instrument Research Institute, National Applied Research Laboratories, Hsinchu 30010, TaiwanDepartment of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanDepartment of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanDepartment of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanInternational College of Semiconductor Technology National Yang Ming Chiao Tung University, Hsinchu 30010, TaiwanDepartment of Electrical and Computer Engineering, University of California, Los Angeles (UCLA), Los Angeles, California 90095, USAThis work explores the integration of strained-channel silicon n-MOSFET with GaN drain using the dual-step selective area epitaxial growth of GaN process, enabling CMOS-compatible, fully selective GaN growth with an excellent GaN/Si interface while adopting a GaN-drain-first manufacturing strategy to accommodate thermal budget constraints. After GaN growth and device fabrication, the Si n-MOSFET with a GaN drain exhibited a strained channel, as the epitaxial GaN acts as a stressor, inducing tensile strain in silicon near the GaN drain and enhancing the device’s low-field mobility. Atomic-resolution scanning transmission electron microscopy with strain mapping confirmed the strain effects, while electrical measurements demonstrated a mobility enhancement from 103.8 to 119.8 cm2 V−1 s−1. The integrated GaN drain offers a high breakdown electric field and excellent optoelectronic properties, making it highly promising for high-power and high-frequency system-on-chip technologies, as well as for integration with laser diodes as a drain. These findings highlight the strong potential of GaN-drain Si n-MOSFETs for radio-frequency power amplifier applications and pave the way for advancements in radar, radio, and optoelectronic circuits and systems.http://dx.doi.org/10.1063/5.0264613
spellingShingle Cheng-Jun Huang
Shuo Hwai
Tsai-Fu Chung
Chien-Nan Hsiao
Bo-Cheng Lin
Hung-Ching Tsai
Chi Huang Lui
Edward Yi Chang
Mau-Chung Frank Chang
Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
AIP Advances
title Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
title_full Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
title_fullStr Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
title_full_unstemmed Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
title_short Strained-channel Si n-MOSFET with GaN-drain via dual-step selective epitaxy for mobility enhancement on Si(100) substrate
title_sort strained channel si n mosfet with gan drain via dual step selective epitaxy for mobility enhancement on si 100 substrate
url http://dx.doi.org/10.1063/5.0264613
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