A Compact 3-Stage Pipelined Hardware Accelerator for Point Multiplication of Binary Elliptic Curves Over GF(2<sup>233</sup>)
This paper presents an area-compact hardware architecture for point multiplication (PM) computation of elliptic curves over binary <inline-formula> <tex-math notation="LaTeX">$GF(2^{233})$ </tex-math></inline-formula> field. We have utilized two approaches with cloc...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10736603/ |
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| Summary: | This paper presents an area-compact hardware architecture for point multiplication (PM) computation of elliptic curves over binary <inline-formula> <tex-math notation="LaTeX">$GF(2^{233})$ </tex-math></inline-formula> field. We have utilized two approaches with clock cycles overhead to reduce the hardware area. First, we have revisited the Montgomery PM algorithm (for hardware implementation) using a memory block <inline-formula> <tex-math notation="LaTeX">$6\times m$ </tex-math></inline-formula> in size. The second approach uses resources of square and multiplier blocks of the arithmetic unit for the computation of a modular inversion. To optimize the critical path of the design, we have used pipeline registers in the arithmetic and logic unit of the proposed PM architecture. We have also proposed re-scheduling point addition and doubling instructions for a 3-stage pipelined architecture. The implementations are provided on an ARTY-7 field-programmable gate array (FPGA) board with an XC7100TCSG324-3 package device. The proposed architecture utilizes 1076 slices, 3269 look-up tables, and 1359 flip-flops. It requires 337880 clock cycles for one PM computation and operates on a maximum of <inline-formula> <tex-math notation="LaTeX">$371MHz$ </tex-math></inline-formula> frequency, necessitating <inline-formula> <tex-math notation="LaTeX">$910.72~\mu s$ </tex-math></inline-formula> for one PM computation. The design’s power consumption is <inline-formula> <tex-math notation="LaTeX">$457mW$ </tex-math></inline-formula>, achieving a maximum throughput of 1Kbps. The comparisons indicate that the proposed accelerator suits applications prioritizing lower hardware resource utilization over computation speed. |
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| ISSN: | 2169-3536 |