A Compact 3-Stage Pipelined Hardware Accelerator for Point Multiplication of Binary Elliptic Curves Over GF(2<sup>233</sup>)

A Compact 3-Stage Pipelined Hardware Accelerator for Point Multiplication of Binary Elliptic Curves Over GF(2<sup>233</sup>)

This paper presents an area-compact hardware architecture for point multiplication (PM) computation of elliptic curves over binary <inline-formula> <tex-math notation="LaTeX">$GF(2^{233})$ </tex-math></inline-formula> field. We have utilized two approaches with cloc...

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Bibliographic Details
Main Authors: Mohammad Mazyad Hazzazi, Muhammad Rashid, Sajjad Shaukat Jamal, Fahad Alblehai, Sameer Nooh, Mujeeb Ur Rehman
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Elliptic curve cryptography
point multiplication
pipeline
hardware
accelerator
architecture
Online Access:https://ieeexplore.ieee.org/document/10736603/
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