Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume
Capacitor-less 2T0C dynamic random-access memory (DRAM) employing oxide semiconductors (OSs) as a channel has great potential in the development of highly scaled three dimensional (3D)-structured devices. However, the use of OS and such device structures presents certain challenges, including the tr...
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| Format: | Article |
| Language: | English |
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IOP Publishing
2025-01-01
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| Series: | International Journal of Extreme Manufacturing |
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| Online Access: | https://doi.org/10.1088/2631-7990/add7a3 |
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| author | Jae-Hyeok Kwag Su-Hwan Choi Daejung Kim Jun-Yeoub Lee Taewon Hwang Hye-Jin Oh Chang-Kyun Park Jin-Seong Park |
| author_facet | Jae-Hyeok Kwag Su-Hwan Choi Daejung Kim Jun-Yeoub Lee Taewon Hwang Hye-Jin Oh Chang-Kyun Park Jin-Seong Park |
| author_sort | Jae-Hyeok Kwag |
| collection | DOAJ |
| description | Capacitor-less 2T0C dynamic random-access memory (DRAM) employing oxide semiconductors (OSs) as a channel has great potential in the development of highly scaled three dimensional (3D)-structured devices. However, the use of OS and such device structures presents certain challenges, including the trade-off relationship between the field-effect mobility and stability of OSs. Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit. Herein, we proposed an IGO (In-Ga-O) channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM. IGO was adopted to achieve high thermal stability above 800 ℃, and the process conditions were optimized to simultaneously obtain a high μ _FE of 90.7 cm ^2 ·V ^−1 ·s ^−1 , positive V _th of 0.34 V, superior reliability, and uniformity. The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation, with the stored voltage varying from 0 V to 1 V at 0.1 V intervals. Furthermore, for stored voltage intervals of 0.1 V and 0.5 V, the refresh time was 10 s and 1 000 s in multi-bit operation; these values were more than 150 and 15 000 times longer than those of the conventional Si channel 1T1C DRAM, respectively. A monolithic stacked 2-line-based 2T0C DRAM was fabricated, and a multi-bit operation was confirmed. |
| format | Article |
| id | doaj-art-5ff40c7b814845faad89b71088d5c621 |
| institution | Kabale University |
| issn | 2631-7990 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IOP Publishing |
| record_format | Article |
| series | International Journal of Extreme Manufacturing |
| spelling | doaj-art-5ff40c7b814845faad89b71088d5c6212025-08-20T03:53:51ZengIOP PublishingInternational Journal of Extreme Manufacturing2631-79902025-01-017505550310.1088/2631-7990/add7a3Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volumeJae-Hyeok Kwag0Su-Hwan Choi1Daejung Kim2Jun-Yeoub Lee3Taewon Hwang4Hye-Jin Oh5Chang-Kyun Park6Jin-Seong Park7https://orcid.org/0000-0002-9070-5666Division of Nanoscale Semiconductor Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDivision of Nanoscale Semiconductor Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDepartment of Display Science and Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDivision of Nanoscale Semiconductor Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDivision of Materials Science and Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDivision of Materials Science and Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaNano Convergence Leader Program for Materials, Parts, and Equipment, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaDivision of Nanoscale Semiconductor Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of Korea; Department of Display Science and Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of Korea; Division of Materials Science and Engineering, Hanyang University , 222 Wangsimni-ro, Seongdong-gu, Seoul 04763, Republic of KoreaCapacitor-less 2T0C dynamic random-access memory (DRAM) employing oxide semiconductors (OSs) as a channel has great potential in the development of highly scaled three dimensional (3D)-structured devices. However, the use of OS and such device structures presents certain challenges, including the trade-off relationship between the field-effect mobility and stability of OSs. Conventional 4-line-based operation of the 2T0C enlarges the entire cell volume and complicates the peripheral circuit. Herein, we proposed an IGO (In-Ga-O) channel 2-line-based 2T0C cell design and operating sequences comparable to those of the conventional Si-channel 1 T1C DRAM. IGO was adopted to achieve high thermal stability above 800 ℃, and the process conditions were optimized to simultaneously obtain a high μ _FE of 90.7 cm ^2 ·V ^−1 ·s ^−1 , positive V _th of 0.34 V, superior reliability, and uniformity. The proposed 2-line-based 2T0C DRAM cell successfully exhibited multi-bit operation, with the stored voltage varying from 0 V to 1 V at 0.1 V intervals. Furthermore, for stored voltage intervals of 0.1 V and 0.5 V, the refresh time was 10 s and 1 000 s in multi-bit operation; these values were more than 150 and 15 000 times longer than those of the conventional Si channel 1T1C DRAM, respectively. A monolithic stacked 2-line-based 2T0C DRAM was fabricated, and a multi-bit operation was confirmed.https://doi.org/10.1088/2631-7990/add7a3capacitor-less 2T0C DRAMcell design and operationatomic layer depositionoxide semiconductormonolithic stacked |
| spellingShingle | Jae-Hyeok Kwag Su-Hwan Choi Daejung Kim Jun-Yeoub Lee Taewon Hwang Hye-Jin Oh Chang-Kyun Park Jin-Seong Park Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume International Journal of Extreme Manufacturing capacitor-less 2T0C DRAM cell design and operation atomic layer deposition oxide semiconductor monolithic stacked |
| title | Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume |
| title_full | Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume |
| title_fullStr | Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume |
| title_full_unstemmed | Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume |
| title_short | Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume |
| title_sort | tailoring the number of lines for igo channel 2t0c dram comparable to conventional 2 line operation 1t1c structure for highly scaled cell volume |
| topic | capacitor-less 2T0C DRAM cell design and operation atomic layer deposition oxide semiconductor monolithic stacked |
| url | https://doi.org/10.1088/2631-7990/add7a3 |
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