Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume

Tailoring the number of lines for IGO-channel 2T0C DRAM comparable to conventional 2-line operation 1T1C structure for highly scaled cell volume

Capacitor-less 2T0C dynamic random-access memory (DRAM) employing oxide semiconductors (OSs) as a channel has great potential in the development of highly scaled three dimensional (3D)-structured devices. However, the use of OS and such device structures presents certain challenges, including the tr...

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Bibliographic Details
Main Authors: Jae-Hyeok Kwag, Su-Hwan Choi, Daejung Kim, Jun-Yeoub Lee, Taewon Hwang, Hye-Jin Oh, Chang-Kyun Park, Jin-Seong Park
Format: Article
Language:English
Published: IOP Publishing 2025-01-01
Series:International Journal of Extreme Manufacturing
Subjects:
capacitor-less 2T0C DRAM
cell design and operation
atomic layer deposition
oxide semiconductor
monolithic stacked
Online Access:https://doi.org/10.1088/2631-7990/add7a3
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https://doi.org/10.1088/2631-7990/add7a3

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