A 16.8 fJ/c-s 8 b 500 MS/s Asynchronous Three-Comparator SAR ADC With Background Comparator-Swapping Offset Calibration in 28 nm CMOS LPP

A 16.8 fJ/c-s 8 b 500 MS/s Asynchronous Three-Comparator SAR ADC With Background Comparator-Swapping Offset Calibration in 28 nm CMOS LPP

This paper presents a novel comparator-swapping background offset calibration method for SAR ADCs, addressing the limitations of previous calibration techniques. The proposed method uses three comparators to eliminate reset time and calibrates offset mismatch based on the LSB conversion, leading to...

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Bibliographic Details
Main Authors: Seunghyun Kim, Yang Azevedo Tavares, Sewon Lee, Minjae Lee
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
ADC based SERDES receiver
three-comparator SAR ADC
background offset calibration
comparator-swapping method
Online Access:https://ieeexplore.ieee.org/document/10964235/
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