Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system
Abstract An electronic circuit that implements a neural network architecture with spike neurons was studied, proposed, and evaluated, primarily considering energy consumption. In this way, CMOS transistors were used to implement neurons, memristors were used to work as synapses, and the proposed net...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-05-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12018 |
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