Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors
It is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as...
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2025-01-01
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| author | Aruzhan Kadyrzhan Kaisarali Kadyrzhan Akhat Bakirov Ibragim Suleimenov |
| author_facet | Aruzhan Kadyrzhan Kaisarali Kadyrzhan Akhat Bakirov Ibragim Suleimenov |
| author_sort | Aruzhan Kadyrzhan |
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| description | It is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>p</mi><mi>k</mi></msub><mo>=</mo><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn><mo>,</mo><mo> </mo><mi>k</mi><mo>=</mo><mn>1</mn><mo>,</mo><mn>2</mn><mo>,</mo><mn>3</mn><mo>,</mo><mn>4</mn></mrow></semantics></math></inline-formula>. Such a set of prime numbers satisfies the criterion <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2</mn><msub><mi>p</mi><mn>1</mn></msub><msub><mi>p</mi><mn>2</mn></msub><msub><mi>p</mi><mn>3</mn></msub><msub><mi>p</mi><mn>4</mn></msub><mo>+</mo><mn>1</mn><mo>=</mo><mi>P</mi></mrow></semantics></math></inline-formula>, where <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>P</mi></semantics></math></inline-formula> is also a prime number. Fulfillment of this criterion ensures the possibility of convenient use of the considered RNS for calculating partial convolutions developed for the convenience of using convolutional neural networks. It is shown that the processor of the proposed type can be based on the use of a set of adders modulo a quasi-Mersenne number, each of which operates independently. A circuit of a modulo <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn></mrow></semantics></math></inline-formula> adder is proposed, which can be called a trigger circuit, since its peculiarity is the existence (at certain values of the summed quantities) of two stable states. The advantage of such a circuit, compared to known analogs, is the simplicity of the design. Possibilities for further development of the proposed approach related to the use of the digital logarithm operation, which allows reducing the operations of multiplication modulo <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn></mrow></semantics></math></inline-formula> to addition operations, are discussed. |
| format | Article |
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| institution | Kabale University |
| issn | 2076-3417 |
| language | English |
| publishDate | 2025-01-01 |
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| series | Applied Sciences |
| spelling | doaj-art-5961734e17684c429ed2d30e7fed9cae2025-01-24T13:20:39ZengMDPI AGApplied Sciences2076-34172025-01-0115274110.3390/app15020741Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial ProcessorsAruzhan Kadyrzhan0Kaisarali Kadyrzhan1Akhat Bakirov2Ibragim Suleimenov3Department of Telecommunication Engineering, Institute of Communications and Space Engineering, Gumarbek Daukeev Almaty University of Power Engineering and Communications, Almaty 050040, KazakhstanNational Engineering Academy of the Republic of Kazakhstan, Almaty 050010, KazakhstanDepartment of Telecommunication Engineering, Institute of Communications and Space Engineering, Gumarbek Daukeev Almaty University of Power Engineering and Communications, Almaty 050040, KazakhstanNational Engineering Academy of the Republic of Kazakhstan, Almaty 050010, KazakhstanIt is shown that a serial-parallel processor, comparable in bit capacity to a 16-bit binary processor, can be implemented based on an algorithm built on the residue number system, a distinctive feature of which is the use of the first four quasi-Mersenne numbers, i.e., prime numbers representable as <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msub><mi>p</mi><mi>k</mi></msub><mo>=</mo><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn><mo>,</mo><mo> </mo><mi>k</mi><mo>=</mo><mn>1</mn><mo>,</mo><mn>2</mn><mo>,</mo><mn>3</mn><mo>,</mo><mn>4</mn></mrow></semantics></math></inline-formula>. Such a set of prime numbers satisfies the criterion <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2</mn><msub><mi>p</mi><mn>1</mn></msub><msub><mi>p</mi><mn>2</mn></msub><msub><mi>p</mi><mn>3</mn></msub><msub><mi>p</mi><mn>4</mn></msub><mo>+</mo><mn>1</mn><mo>=</mo><mi>P</mi></mrow></semantics></math></inline-formula>, where <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi>P</mi></semantics></math></inline-formula> is also a prime number. Fulfillment of this criterion ensures the possibility of convenient use of the considered RNS for calculating partial convolutions developed for the convenience of using convolutional neural networks. It is shown that the processor of the proposed type can be based on the use of a set of adders modulo a quasi-Mersenne number, each of which operates independently. A circuit of a modulo <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn></mrow></semantics></math></inline-formula> adder is proposed, which can be called a trigger circuit, since its peculiarity is the existence (at certain values of the summed quantities) of two stable states. The advantage of such a circuit, compared to known analogs, is the simplicity of the design. Possibilities for further development of the proposed approach related to the use of the digital logarithm operation, which allows reducing the operations of multiplication modulo <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><msup><mn>2</mn><mi>k</mi></msup><mo>+</mo><mn>1</mn></mrow></semantics></math></inline-formula> to addition operations, are discussed.https://www.mdpi.com/2076-3417/15/2/741quasi-Mersen numberstrigger addereffective bit depth of addercomputing performanceparallel-serial computingresidue number system (RNS) |
| spellingShingle | Aruzhan Kadyrzhan Kaisarali Kadyrzhan Akhat Bakirov Ibragim Suleimenov Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors Applied Sciences quasi-Mersen numbers trigger adder effective bit depth of adder computing performance parallel-serial computing residue number system (RNS) |
| title | Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors |
| title_full | Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors |
| title_fullStr | Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors |
| title_full_unstemmed | Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors |
| title_short | Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors |
| title_sort | prospects for the use of quasi mersen numbers in the design of parallel serial processors |
| topic | quasi-Mersen numbers trigger adder effective bit depth of adder computing performance parallel-serial computing residue number system (RNS) |
| url | https://www.mdpi.com/2076-3417/15/2/741 |
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