A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product
The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors....
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2014/453675 |
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| author | Kunwar Singh Satish Chandra Tiwari Maneesha Gupta |
| author_facet | Kunwar Singh Satish Chandra Tiwari Maneesha Gupta |
| author_sort | Kunwar Singh |
| collection | DOAJ |
| description | The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes. |
| format | Article |
| id | doaj-art-5926d107bee3496c9885dde79f24ad8a |
| institution | Kabale University |
| issn | 2356-6140 1537-744X |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Scientific World Journal |
| spelling | doaj-art-5926d107bee3496c9885dde79f24ad8a2025-02-03T01:02:25ZengWileyThe Scientific World Journal2356-61401537-744X2014-01-01201410.1155/2014/453675453675A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area ProductKunwar Singh0Satish Chandra Tiwari1Maneesha Gupta2Department of Electrical Engineering, Delhi Technological University, Room No. FW1-SF1, EED, DTU, New Delhi 110042, IndiaDivision of ECE, Netaji Subhas Institute of Technology (NSIT), University of Delhi, Sector 3, Dwarka, New Delhi 110078, IndiaDivision of ECE, Netaji Subhas Institute of Technology (NSIT), University of Delhi, Sector 3, Dwarka, New Delhi 110078, IndiaThe paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.http://dx.doi.org/10.1155/2014/453675 |
| spellingShingle | Kunwar Singh Satish Chandra Tiwari Maneesha Gupta A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product The Scientific World Journal |
| title | A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product |
| title_full | A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product |
| title_fullStr | A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product |
| title_full_unstemmed | A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product |
| title_short | A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product |
| title_sort | modified implementation of tristate inverter based static master slave flip flop with improved power delay area product |
| url | http://dx.doi.org/10.1155/2014/453675 |
| work_keys_str_mv | AT kunwarsingh amodifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct AT satishchandratiwari amodifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct AT maneeshagupta amodifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct AT kunwarsingh modifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct AT satishchandratiwari modifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct AT maneeshagupta modifiedimplementationoftristateinverterbasedstaticmasterslaveflipflopwithimprovedpowerdelayareaproduct |