Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip
In the finish stage of the chip physical design, in order to meet the metal density design rules, dummy metal fill needs to be added. The dummy metal fill generates external parasitic capacitances, which will deteriorate chip timing results. In process nodes above 40 nm, timing deviation caused by t...
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| Format: | Article |
| Language: | zho |
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National Computer System Engineering Research Institute of China
2022-06-01
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| Series: | Dianzi Jishu Yingyong |
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| Online Access: | http://www.chinaaet.com/article/3000150250 |
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| _version_ | 1849421065951903744 |
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| author | Wang Qiushi Meng Shaopeng Wu Hongqiang |
| author_facet | Wang Qiushi Meng Shaopeng Wu Hongqiang |
| author_sort | Wang Qiushi |
| collection | DOAJ |
| description | In the finish stage of the chip physical design, in order to meet the metal density design rules, dummy metal fill needs to be added. The dummy metal fill generates external parasitic capacitances, which will deteriorate chip timing results. In process nodes above 40 nm, timing deviation caused by these external parasitic capacitances is about 0.12%, even smaller than the mismatch between STA and SPICE simulation, we usually ignore it. However, this timing deviation must be repaired in advanced process nodes with FinFET structure. Taking a industrial DSP process chip with FinFET structure as an example, this paper uses QRC to compare the parasitic capacitance changes before and after adding dummy metal fill; uses Tempus to analyze the reasons for the timing deviation of the chip; finally proposes a method for repairing timing deviation based on Innovus, the timing result is verified by signoff. This method effectively improves the efficiency of timing closure. |
| format | Article |
| id | doaj-art-51fbee15dbf44642a0911e248c499c2b |
| institution | Kabale University |
| issn | 0258-7998 |
| language | zho |
| publishDate | 2022-06-01 |
| publisher | National Computer System Engineering Research Institute of China |
| record_format | Article |
| series | Dianzi Jishu Yingyong |
| spelling | doaj-art-51fbee15dbf44642a0911e248c499c2b2025-08-20T03:31:33ZzhoNational Computer System Engineering Research Institute of ChinaDianzi Jishu Yingyong0258-79982022-06-01486424410.16157/j.issn.0258-7998.2123533000150250Analysis and repair of timing deviation caused by filling dummy metal in advanced process chipWang Qiushi0Meng Shaopeng1Wu Hongqiang2Anhui Siliepoch Technology Co.，Ltd.，Hefei 230031，ChinaAnhui Siliepoch Technology Co.，Ltd.，Hefei 230031，ChinaAnhui Siliepoch Technology Co.，Ltd.，Hefei 230031，ChinaIn the finish stage of the chip physical design, in order to meet the metal density design rules, dummy metal fill needs to be added. The dummy metal fill generates external parasitic capacitances, which will deteriorate chip timing results. In process nodes above 40 nm, timing deviation caused by these external parasitic capacitances is about 0.12%, even smaller than the mismatch between STA and SPICE simulation, we usually ignore it. However, this timing deviation must be repaired in advanced process nodes with FinFET structure. Taking a industrial DSP process chip with FinFET structure as an example, this paper uses QRC to compare the parasitic capacitance changes before and after adding dummy metal fill; uses Tempus to analyze the reasons for the timing deviation of the chip; finally proposes a method for repairing timing deviation based on Innovus, the timing result is verified by signoff. This method effectively improves the efficiency of timing closure.http://www.chinaaet.com/article/3000150250advanced process nodephysical designdummy metal fillparasitic capacitancetiming repair |
| spellingShingle | Wang Qiushi Meng Shaopeng Wu Hongqiang Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip Dianzi Jishu Yingyong advanced process node physical design dummy metal fill parasitic capacitance timing repair |
| title | Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| title_full | Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| title_fullStr | Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| title_full_unstemmed | Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| title_short | Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| title_sort | analysis and repair of timing deviation caused by filling dummy metal in advanced process chip |
| topic | advanced process node physical design dummy metal fill parasitic capacitance timing repair |
| url | http://www.chinaaet.com/article/3000150250 |
| work_keys_str_mv | AT wangqiushi analysisandrepairoftimingdeviationcausedbyfillingdummymetalinadvancedprocesschip AT mengshaopeng analysisandrepairoftimingdeviationcausedbyfillingdummymetalinadvancedprocesschip AT wuhongqiang analysisandrepairoftimingdeviationcausedbyfillingdummymetalinadvancedprocesschip |