Analysis and repair of timing deviation caused by filling dummy metal in advanced process chip
In the finish stage of the chip physical design, in order to meet the metal density design rules, dummy metal fill needs to be added. The dummy metal fill generates external parasitic capacitances, which will deteriorate chip timing results. In process nodes above 40 nm, timing deviation caused by t...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | zho |
| Published: |
National Computer System Engineering Research Institute of China
2022-06-01
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| Series: | Dianzi Jishu Yingyong |
| Subjects: | |
| Online Access: | http://www.chinaaet.com/article/3000150250 |
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