Dual Strategy of Electroless Metal Deposition and Surface Silylation Toward Scalable Low-Temperature Hybrid Bonding for Advanced Packaging Applications

Dual Strategy of Electroless Metal Deposition and Surface Silylation Toward Scalable Low-Temperature Hybrid Bonding for Advanced Packaging Applications

The growing demand for high-performance computing and compact electronics has driven the transition toward advanced three-dimensional (3D) packaging technologies. Traditional packaging technologies, such as micro-bump interconnections, face limitations in achieving sub-micrometer pitches, prompting...

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Bibliographic Details
Main Authors: Zambaga Otgonbayar, Jeoung Han Kim, Jinsung Rho, Jeong-Chul Kim, Jungchul Noh, Jeonghun Kim, Seong-Ho Yoon, Chang-Min Yoon
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
Subjects:
Three-dimensional packaging
low-temperature bonding
metal electroless deposition
silylation
Cu/SiO₂ hybrid bonding
Online Access:https://ieeexplore.ieee.org/document/11071665/
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Summary:The growing demand for high-performance computing and compact electronics has driven the transition toward advanced three-dimensional (3D) packaging technologies. Traditional packaging technologies, such as micro-bump interconnections, face limitations in achieving sub-micrometer pitches, prompting the development of alternative bonding strategies. Among them, Cu/SiO2 hybrid bonding (HB) has emerged as a promising method for enabling fine-pitch, high-density interconnects in next-generation semiconductor packaging. In this study, a reliable low-temperature Cu/SiO2 HB process was developed by combining metal electroless deposition (ELD) on sub-micron pitch Cu pads with selective surface functionalization of the SiO2 dielectric layer using silane. The ELD process facilitated uniform and selective Au deposition on Cu, acting as a diffusion metal that maintained interfacial stability during bonding. Conclusively, the SiO2 surface was modified with (3-aminopropyl)triethoxysilane (APTES), which formed strong covalent networks through silane polymerization, enhancing adhesion at the dielectric interface. This dual modification strategy facilitated direct Cu&#x2013;Cu bonding and robust SiO2&#x2013;SiO2 adhesion, resulting in a defect-free interface without voids or delamination. The bonding was conducted at a low-temperature of <inline-formula> <tex-math notation="LaTeX">$250~^{\circ }$ </tex-math></inline-formula>C, thereby minimizing thermal stress typically associated with conventional high-temperature bonding processes. These result clearly demonstrates a practical and scalable method for achieving low-temperature Cu/SiO2 HB, contributing to the advancement of 3D integration in semiconductor packaging.
ISSN:2169-3536

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